This invention relates to an auto-reset circuit used to initialize an electronic circuit when the electronic circuit is powered up, or when its power supply is momentarily interrupted.
When a complex electronic device such as a large-scale-integrated (LSI) circuit is powered up, it must generally be reset by placing its internal circuits in certain initial states. The device must also be reset if its power supply is interrupted during operation, as sometimes happens due to temporary conditions. For these purposes, LSI and other devices often have an auto-reset circuit that detects the rise of the power supply and generates an internal reset signal.
Many types of auto-reset circuits can be found in the prior art. One of the simplest comprises a resistor and capacitor coupled in series between the two power-supply terminals, which are commonly referred to as power and ground, or V.sub.DD and V.sub.SS. The reset signal is taken from a point between the resistor and capacitor. At power-up the reset signal starts with the value of one of the two power-supply potentials, then changes to the value of the other as the capacitor charges. The reset signal can be used directly, or it can be used to drive an output stage such as an inverter or Schmitt trigger. A disadvantage of this simple auto-reset circuit is that it fails to produce a reset signal if the supply voltage rises slowly in comparison to the resistor-capacitor time constant, or if power is interrupted for an interval that is brief in relation to that time constant.
To overcome the disadvantages of this simple circuit, many auto-reset circuits incorporating active elements have been developed. The one that comes closest to the present invention has a p-channel metal-oxide-semiconductor field-effect transistor (referred to below as a P-MOSFET) and a resistor coupled in series between the power-supply terminals, the source of the P-MOSFET being coupled to V.sub.DD and its drain to the resistor. An n-channel metal-oxide-semiconductor field-effect transistor (referred to below as an N-MOSFET) and another resistor are also coupled in series between the power-supply terminals, the source of the N-MOSFET transistor being coupled to V.sub.SS and its drain to the resistor. The gates of both the P-MOSFET and N-MOSFET are coupled to the drain of the P-MOSFET. The reset signal is output from the drain of the N-MOSFET.
This circuit produces a reset signal that is initially high, but goes low when the supply voltage reaches a value equal to the sum of the threshold voltages of the two MOSFETs. With the traditional five-volt power supply, the reset signal is typically output while the supply voltage rises from zero to about 1.4 V, then released as the supply voltage rises from 1.4 V to a steady-state 5 V.
The recent trend toward three-volt operation has created a problem for this auto-reset circuit, however. The problem arises, for example, during device tests carried out prior to shipment to the customer. Consider a device specified to operate reliably on a 3.0-V .+-.10% power supply over a temperature range of -40.degree. C. to +85.degree. C. The nominal transistor threshold voltage is 0.7 V, but there is a variability of about .+-.0.25 V inherent in the fabrication process, and further variability results from the temperature dependence of the threshold voltage, so within the above temperature range the threshold voltage may be as high as 1.2 V. If both the P-MOSFET and N-MOSFET have this threshold voltage, then the reset signal will not be released until the supply voltage reaches at least 2.4 V.
This would not necessarily be a problem if tests were carried out with supply voltages between 2.7 V and 3.3 V, but to prevent degradation of circuit elements, tests may be performed at a reduced supply voltage such as 2.4 V. When the device is powered up to this voltage, the auto-reset circuit may fail to release the reset signal, causing the device to be rejected as defective. To allow a reasonable margin in such tests, the auto-reset circuit needs to release the reset signal at about 1.9 V.
The problem becomes even more serious at lower supply voltages, such as the 1.8 V supply voltage employed in devices driven by two-nickel-cadmium cells. For such devices the auto-reset circuit described above is completely unsatisfactory.
Another problem that occurs in device testing is that current flow through the above auto-reset circuit cannot be reduced to zero. One of the tests performed to detect photolithography defects and other defects is a measurement of static current consumption (I.sub.DD). The presence of current flow through the auto-reset circuit impairs the precision of this measurement, because the exact amount of current flowing through the auto-reset circuit is unknown. Also, it becomes impossible to characterize the device down to extremely small current values. Thus the test fails to screen out devices having minor defects that may lead to failure in the field.
Yet another problem of the above auto-reset circuit is that in some cases it may generate a reset signal with an inadequate pulse width, or fail to output a reset signal at all. This problem occurs not only at power-up, but also when the supply voltage drops momentarily during operation, then recovers. It occurs particularly when the supply voltage rises rapidly (in a few hundred nanoseconds, for example), and the reset signal must drive a significant capacitive load.
In many devices the internal reset signal does drive a significant capacitive load, because there are many internal circuits to be reset. If the reset signal is routed to those circuits directly, the capacitance of the signal-line wiring is large. If buffers are used, the reset signal must drive the input capacitance of the buffers. A capacitive load on the order of half a picofarad is typical. If the resistor through which the reset signal is output has sufficient resistance to hold current flow through the auto-reset circuit to about ten microamperes during the steady state, and the power supply rises to five volts in a few hundred nanoseconds, then the reset signal will be released while the capacitive load is still charging and the reset signal is still inactive.
This problem could be alleviated by reducing the resistance value of the resistor, but then more current would flow through the circuit during steady-state operation. If the current flow is too high, problems such as excessive power consumption and battery drain arise.